In the information processing system, such as a computer unit and a network unit, various service processing and protocol processing are performed in response to a request from a client terminal. A redundancy configuration and redundancy control are required to ensure the reliability of a central processing unit (CPU) within the system performing the service processing and the protocol processing.
FIG. 1 shows an example of the information processing system configuration for performing general CPU redundancy control. The configuration and the redundancy control operation are described below.
In the information processing system shown in FIG. 1, the active side and the standby side are respectively provided with a CPU, allowing the service to the client to be continued even during one CPU failure.
Specifically, the information processing system shown in FIG. 1 includes, firstly, a PCI (peripheral component interconnect) network interface 1041 for accepting a service request from the client terminal 301. This system also includes the CPU 1011, a memory controller hub 1021, and a memory 1031 as the active side configuration for processing the service request. This system also includes the CPU 1012, a memory controller hub 1022, and a memory 1032 as the standby side configuration used as a substitute during a failure on the active side.
The information processing system further includes a PCI bus switch 107 for performing exclusive connection control with respect to the active side and the standby side in the PCI network interface 1041. This system also includes PCI network interfaces 1042 and 1043 which are used as data passages of synchronization processing on the active side and the standby side, respectively.
In the configuration, the service request from the client is generally accepted through an input/output (I/O) connection interface. However, the PCI or PCI express device does not permit concurrent connections of a plurality of CPUs. Hence, a structure to perform exclusive control becomes necessary when establishing connection with the plurality of CPUs needed in the redundancy configuration, as in the case of the configuration described above.
FIG. 2 shows the internal configuration of the PCI network interface 1041 for accepting the service request from the client terminal 301. The PCI network interface 1041 includes a media access controller 10414 for processing network frames, a packet receive memory 10412 used upon receipt of a packet, and a packet send memory 10413 used when sending a packet.
The PCI network interface 1041 also includes a PCI bus controller 10411 for connection to a PCI connection interface, a direct memory access (DMA) controller 10417 for performing control during data transfer when sending/receiving a packet, a DMA control register 10416 as a control register thereof, and a PCI configuration register 10415 for setting an interface. All of the service request data from the client terminal are sent/received through the interface. When sending/receiving the data, the data read/write processing with respect to the CPUs are under control of the DMA controller 10417.
FIG. 3 shows a software stack operating on the active side CPU 1011. Similarly, FIG. 4 shows a software stack operating on the standby side CPU 1012. Service processing for processing the request from the client terminal 301, and the redundancy processing for performing redundancy control on the active side and the standby side are operated on these softwares. FIGS. 5 and 6 show memory address states controlled by the CPUs 1011 and 1012, respectively. Hereinafter, a series of operations of these CPUs 1011 and 1012, namely, the softwares that operate on these CPUs are described with reference to FIGS. 7A-7D and FIGS. 8A-8D. FIGS. 7A-7D are flowcharts illustrating the operations of the active side CPU 1011. FIGS. 8A-8D are flowcharts illustrating the operations of the standby side CPU 1012.
The software incorporated into the active side CPU 1011 shown in FIG. 3 configures an operating system 90 and a redundancy service application 80. On the operating system 90, in order to enable the redundancy service application 80 to send/receive data, a PCIDMA control section 903 operates which enables basic data send/receive by controlling a DMA controller of a PCI network interface card. Also, a network driver 902 for performing network packet processing, and a TCP/IP protocol stack 901 for performing network protocol processing, such as packet reach guarantee, operate on the operation system 90.
The redundancy service application 80 executes the following processing. That is, a packet send/receive processing section 802 receives a service request packet 8022 through the operating system 90 (step S101), and a service processing section 801 performs service processing and returns a service response packet 8021 to the client. On that occasion, the service request packet 8022 is subjected to DMA transfer (step S102), and then stored and processed in the main memory 1031 of the CPU 1011 (step S103). FIG. 5 shows the state of the main memory 1031 controlled by the CPU 1011, and indicates a memory region of the memory 1031. With respect to the main memory 1031, a receive packet is stored in a space “0×5100−5200,” and a send packet is stored in a space “0×5000−0×5100.”
The active side software performs redundancy control with the standby side in the process of the service processing. The redundancy control is for controlling so that the service can be taken over in the event of the CPU failure. Specifically, the software controls so that every time the packet send/receive processing section 802 receives a packet, a packet mirroring section 804 sends a service request copy packet 8041 to the standby side (refer to step S104, and steps S1001 to S1006 in FIG. 7B). In order to establish the synchronization of the service processing, the service processing section 801 controls so that a service synchronization processing section 803 sends a service processing phase synchronization packet 8031 to the standby side (refer to steps S105 and S106, and steps S1011 to S1016 in FIG. 7C). Then, a service processing phase synchronization response packet 8032 is received on the standby side, and the service processing is progressed on the active side upon confirmation of the synchronization establishment.
Thereafter, upon completion of the service processing on the active side (step S107), a service response packet 8021 as the processing result is sent to the client terminal 301 (steps S108, S109, and S110).
Hereat, the alive state of the active side is monitored all the time by a redundancy system alive monitoring section 807 of the standby side, a redundancy system dead/alive response section 805 periodically receives a keep-alive management packet 8051 from the standby side, and sends a dead/alive response packet 8052 (refer to steps S1021 to S1025 in FIG. 7D).
The standby side performs receive processing of the service request copy packet 8041 and the service processing phase synchronization packet 8031 sent from the active side as described above (refer to steps S121 and S122, steps S1031 to S1035 in FIG. 8B, and steps S1041 to S1046 in FIG. 8C). The redundancy system alive monitoring section 807 of the standby side confirms whether the active side is alive (refer to step S123, and steps S1051 to S1057 in FIG. 8D). When the dead/alive response packet 8052 is not received, a service processing redundancy control section 806 controls redundancy switching between the active side and the standby side (step S124).
The data related to the service request copy packet 8041 and service processing steps are stored at “0×8100−8200” and “0×8300−0×8400” in the memory 1031, as shown in FIG. 5, and the data are sent to the standby side. Similarly, various types of data sent from the active side are stored on the standby side, as shown in FIG. 6. Specifically, a service receive copy packet and a master dead/alive state management area are stored at “0×8100−8200” and “0×8200−8300” in the memory 1032, respectively.
In the redundancy switching control, according to a PCI bus switch setting 8061, a PCI bus switch 107 performs connection switching of a PCI network interface 1041 from a memory controller hub 1021 to a memory controller hub 1022. This causes the CPU 1012 to receive the service request from the client, and the standby side service processing section 801 controls to take over the service processing by using the information of the service request copy packet 8041 and the information of the service processing phase synchronization packet 8031 (steps S125 to S130).
Patent Document
                Patent document 1:. Japanese Unexamined Patent Application Publication No. 2006-195821. Non-patent Document        Non-patent document 1: Multi-Root I/O Virtualization and Sharing Specification Revision 1.0, PCI-SIG, May 12, 2008, pp. 29        
However, in the redundancy control described above, the data sending for the redundancy processing is required to ensure perfect data reachability. It is therefore necessary to use TCP processing through the TCP/IP protocol stack 901, the network driver 902, the PCIDMA control 903, and the PCI network interface 1042. This places a load on the CPUs, making it difficult to achieve high speed synchronization. Especially, there is the following problem that when the CPU 1011 performs the service processing, the copy processing of the service request packet necessary for the redundancy control, and the sending of the packet thereof double the CPU process load related to the packet sending and receiving, thus considerably deteriorating the system performance of the service processing.
The service request packet 8022 sent from the client terminal 301 is transmitted as the service request copy packet 8041 to the standby side under the redundancy control. Therefore, if a failure occurs in the active side CPU 1011, regarding the information not yet IS sent as the service request copy packet 8041, the data within the memory 1031 cannot be extracted. Thus, there arises the following problem that the packet information are lost, failing to perform perfect redundancy control.